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» Building heterogeneous reconfigurable systems using threads
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ERSA
2006
128views Hardware» more  ERSA 2006»
13 years 9 months ago
Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture
Mobile wireless communication systems become multi-mode systems. These future mobile systems employ multiple wireless communication standards, which are different by means of algor...
Gerard K. Rauwerda, Gerard J. M. Smit, Casper R. W...
FPGA
1999
ACM
130views FPGA» more  FPGA 1999»
13 years 12 months ago
Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition...
Frank Heile, Andrew Leaver
PERCOM
2006
ACM
14 years 7 months ago
Omero: Ubiquitous User Interfaces in the Plan B Operating System
It is difficult to build user interfaces that must be distributed over a set of dynamic and heterogeneous I/O devices. This difficulty increases when we want to split, merge, repl...
Francisco J. Ballesteros, Gorka Guardiola Muzquiz,...
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
14 years 4 months ago
Run-Time Execution of Reconfigurable Hardware in a Java Environment
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...
ARC
2010
Springer
186views Hardware» more  ARC 2010»
13 years 11 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan