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» CAD Directions for High Performance Asynchronous Circuits
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APCSAC
2005
IEEE
14 years 3 months ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope
WEBNET
2001
13 years 11 months ago
Electronically Assisting Communication for Health Professionals
: New information and computing technologies offer cost efficient and effective learning opportunities for health care professionals. The Assisted Electronic Communication project ...
Peter Scott, Fiona Brooks, Kevin Quick, Maria Maci...
EMSOFT
2010
Springer
13 years 7 months ago
From high-level component-based models to distributed implementations
Constructing correct distributed systems from their high-level models has always been a challenge and often subject to serious errors because of their non-deterministic and non-at...
Borzoo Bonakdarpour, Marius Bozga, Mohamad Jaber, ...
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 3 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ASPDAC
2009
ACM
152views Hardware» more  ASPDAC 2009»
14 years 4 months ago
A novel Toffoli network synthesis algorithm for reversible logic
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
Yexin Zheng, Chao Huang