Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...
In this paper we disprove the belief widespread within the computer graphics community that Catmull-Clark subdivision surfaces cannot be evaluated directly without explicitly subd...
The Virtual Reality Modeling Language (VRML) and the World Wide Web (WWW) offer new opportunities to communicate an architect’s design intent throughout the design process. We h...
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topo...
Proof AnimationTM is a family of products for animating discrete event simulations. Proof is available in a variety of versions, including an inexpensive, student version, midsize...