4 search results - page 1 / 1 » CCHIME: A Cache Coherent Hybrid Interconnected Memory Extens... |
IPPS
1992
IEEE
13 years 11 months ago
1992
IEEE
This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent c...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
TC
2011
13 years 1 months ago
2011
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
IPPS
2000
IEEE
13 years 11 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...