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ISCAS
2005
IEEE
131views Hardware» more  ISCAS 2005»
14 years 4 months ago
A low-complexity scanned-array 3D IIR frequency-planar filter
— We extend a 3D differential-operator-based filter architecture to a 3D IIR FPGA filter circuit implementation employing a recently proposed scanned-array method, which uses a s...
Arjuna Madanayake, Leonard T. Bruton
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 4 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
ICCAD
1998
IEEE
83views Hardware» more  ICCAD 1998»
14 years 3 months ago
Signature hiding techniques for FPGA intellectual property protection
John Lach, William H. Mangione-Smith, Miodrag Potk...
DAC
2007
ACM
14 years 12 months ago
Enhancing FPGA Performance for Arithmetic Circuits
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par...
FPL
2008
Springer
163views Hardware» more  FPL 2008»
14 years 13 days ago
Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenc...