— We extend a 3D differential-operator-based filter architecture to a 3D IIR FPGA filter circuit implementation employing a recently proposed scanned-array method, which uses a s...
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par...
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenc...