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ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
15 years 9 months ago
Interconnect capacitance estimation for FPGAs
Abstract—The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and...
Jason Helge Anderson, Farid N. Najm
FCCM
2004
IEEE
96views VLSI» more  FCCM 2004»
15 years 7 months ago
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching
In this paper we advocate the use of pre-decoding for CAM-based pattern matching. We implement an FPGA based sub-system for NIDS (Snort) pattern matching using a combination of te...
Ioannis Sourdis, Dionisios N. Pnevmatikatos
EURODAC
1995
IEEE
133views VHDL» more  EURODAC 1995»
15 years 7 months ago
Tree restructuring approach to mapping problem in cellular-architecture FPGAs
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Nav...
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
15 years 7 months ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
AHS
2006
IEEE
138views Hardware» more  AHS 2006»
15 years 10 months ago
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures
Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has sh...
Emanuele Stomeo, Tatiana Kalganova, Cyrille Lamber...