416 search results - page 73 / 84 » CMOL FPGA circuits |
FPL
2005
Springer
14 years 3 months ago
2005
Springer
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
FPL
2005
Springer
14 years 3 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
FPL
2004
Springer
14 years 3 months ago
2004
Springer
Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement s...
ICES
2001
Springer
14 years 2 months ago
2001
Springer
A system for intrinsic hardware evolution of analog electronic circuits is presented. It consists of a VLSI chip featuring 16 × 16 programmable transistor cells, an FPGA based PCI...
ISMVL
1998
IEEE
14 years 2 months ago
1998
IEEE
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode ...