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EURODAC
1995
IEEE
182views VHDL» more  EURODAC 1995»
13 years 11 months ago
Delay modelling improvement for low voltage applications
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
Jean Michel Daga, Michel Robert, Daniel Auvergne
ISCAS
2003
IEEE
79views Hardware» more  ISCAS 2003»
14 years 27 days ago
Movement of small amplitude parts in a coupled chaotic system
We investigate the movement of small amplitude parts in a coupled chaotic system. The system consists of chaotic circuits using CMOS ring oscillators and capacitors as coupling el...
Yasuteru Hosokawa, Yoshifumi Nishio
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
14 years 2 months ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
ICCD
1996
IEEE
134views Hardware» more  ICCD 1996»
13 years 11 months ago
Pausible Clocking: A First Step Toward Heterogeneous Systems
This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In thi...
Kenneth Y. Yun, Ryan P. Donohue