13 search results - page 1 / 3 » CMP-aware Maze Routing Algorithm for Yield Enhancement |
ASPDAC
2005
ACM
14 years 8 months ago
2005
ACM
- Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via afte...
ISVLSI
2007
IEEE
15 years 19 days ago
2007
IEEE
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
ISPD
1999
ACM
14 years 10 months ago
1999
ACM
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
TCAD
2008
14 years 6 months ago
2008
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
DAC
2004
ACM
14 years 11 months ago
2004
ACM
As the technology migrates into the deep submicron manufacturing (DSM) era, the critical dimension of the circuits is getting smaller than the lithographic wavelength. The unavoid...