869 search results - page 124 / 174 » Cache Architectures for Reconfigurable Hardware |
SIGMETRICS
2011
ACM
12 years 10 months ago
2011
ACM
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading)...
ISCA
2002
IEEE
14 years 16 days ago
2002
IEEE
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...