869 search results - page 136 / 174 » Cache Architectures for Reconfigurable Hardware |
CF
2005
ACM
13 years 9 months ago
2005
ACM
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....