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DAC
2001
ACM
14 years 8 months ago
Using Texture Mapping with Mipmapping to Render a VLSI Layout
This paper presents a method of using texture mapping with mipmapping to render a VLSI layout. Texture mapping is used to save already rasterized areas of the layout from frame to...
Jeff Solomon, Mark Horowitz
APCSAC
2006
IEEE
14 years 1 months ago
Using Branch Prediction Information for Near-Optimal I-Cache Leakage
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the perform...
Sung Woo Chung, Kevin Skadron
IEEEPACT
2005
IEEE
14 years 1 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
CF
2010
ACM
14 years 19 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 1 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...