869 search results - page 146 / 174 » Cache Architectures for Reconfigurable Hardware |
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
CAV
2006
Springer
13 years 11 months ago
2006
Springer
Fast is a tool designed for the analysis of counter systems, i.e. automata extended with unbounded integer variables. Despite the reachability set is not recursive in general, Fast...
SIGCOMM
2010
ACM
13 years 7 months ago
2010
ACM
Traditionally, in-network services like firewall, proxy, cache, and transcoders have been provided by dedicated hardware middleboxes. A recent trend has been to remove the middleb...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling ...
IEEEPACT
2003
IEEE
14 years 24 days ago
2003
IEEE
We present a technique for reducing the power dissipation in the course of writebacks and committments in a datapath that uses a dedicated architectural register file (ARF) to hol...