Source-level timing annotation for fast and accurate TLM computation model generation

This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling (TLM) approach is widely adopted now for system modeling and simulation speed improvement, timing estimation accuracy often is compromised. To have reliable and accurate estimation results at system level, we propose a timing annotation method for accurate TLM computation model generation considering processor architecture with pipeline and cache structures, which are challenging but critical to accurate timing estimation. The experiments show that our results are within 2% of cycle accurate results and the approach is three orders faster than conventional ISS approaches.

• Type: Journal
• Year: 2010
• Where: ASPDAC
• Authors: Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay
• Keywords: Accurate, Accurate Transaction Level, ASPDAC 2010, Hardware, Timing Annotation Method