869 search results - page 147 / 174 » Cache Architectures for Reconfigurable Hardware |
INFOCOM
1992
IEEE
13 years 11 months ago
1992
IEEE
The current Internet is based on a stateless (datagram) architecture. However, many recent proposals rely on the maintenance of state information within network routers, leading t...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
SIGMOD
1991
ACM
13 years 11 months ago
1991
ACM
This paper presents an architecture for a persistent object store in which multi-level storage is explicitly included. Traditionally, DBMSs have assumed that all accessible data r...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...