869 search results - page 150 / 174 » Cache Architectures for Reconfigurable Hardware |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
Traditionally, tracking systems require dedicated hardware to handle the computational demands and input/output rates imposed by real-time video sources. An alternative presented i...