869 search results - page 165 / 174 » Cache Architectures for Reconfigurable Hardware |
CODES
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Server consolidation is becoming an increasingly popular technique to manage and utilize systems. This paper develops CMP memory systems for server consolidation where most sharin...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
EDCC
2006
Springer
13 years 11 months ago
2006
Springer
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
ANCS
2007
ACM
13 years 11 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...