869 search results - page 80 / 174 » Cache Architectures for Reconfigurable Hardware |
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...