Sciweavers

158 search results - page 16 / 32
» Cache Based Power Analysis Attacks on AES
Sort
View
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
14 years 1 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
CHES
2005
Springer
123views Cryptology» more  CHES 2005»
14 years 2 months ago
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
We demonstrate that masking a block cipher implementation does not sufficiently improve its security against side-channel attacks. Under exactly the same hypotheses as in a Differ...
Eric Peeters, François-Xavier Standaert, Ni...
INFOCOM
2010
IEEE
13 years 7 months ago
An Attack-Defense Game Theoretic Analysis of Multi-Band Wireless Covert Timing Networks
—We discuss malicious interference based denial of service (DoS) attacks in multi-band covert timing networks using an adversarial game theoretic approach. A covert timing networ...
Santhanakrishnan Anand, Shamik Sengupta, Rajarathn...
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
14 years 8 days ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
ICS
2009
Tsinghua U.
14 years 1 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...