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CASES
2005
ACM
13 years 9 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
14 years 7 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
CORR
2011
Springer
181views Education» more  CORR 2011»
12 years 11 months ago
Garbage Collection for Multicore NUMA Machines
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated p...
Sven Auhagen, Lars Bergstrom, Matthew Fluet, John ...