67 search results - page 6 / 14 » Cache Performance of Combinator Graph Reduction |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
JCP
2007
13 years 7 months ago
2007
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
ICDAR
2009
IEEE
13 years 5 months ago
2009
IEEE
Combining classifier methods have shown their effectiveness in a number of applications. Nonetheless, using simultaneously multiple classifiers may result in some cases in a reduc...
LCTRTS
2005
Springer
14 years 1 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
IPPS
2003
IEEE
14 years 27 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...