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ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
13 years 11 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 7 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
PAM
2009
Springer
14 years 5 months ago
Revisiting Route Caching: The World Should Be Flat
Internet routers’ forwarding tables (FIBs), which must be stored in expensive fast memory for high-speed packet forwarding, are growing quickly in size due to increased multihomi...
Changhoon Kim, Matthew Caesar, Alexandre Gerber, J...
ACISICIS
2005
IEEE
14 years 4 months ago
An Effective Cache Overlapping Storage Structure for SMT Processors
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
Liqiang He, Zhiyong Liu
DEEC
2005
IEEE
14 years 4 months ago
Using Semantic Information to Improve Transparent Query Caching for Dynamic Content Web Sites
In this paper, we study the use of semantic information to improve performance of transparent query caching for dynamic content web sites. We observe that in dynamic content web a...
Gokul Soundararajan, Cristiana Amza