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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
14 years 21 days ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 11 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
PVLDB
2010
142views more  PVLDB 2010»
13 years 5 months ago
Distributed Caching Platforms
With the advances in processing, memory, and connectivity technologies, applications are becoming increasingly distributed, data-centric, and web based. These applications demand ...
Anil Nori
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
COMCOM
2002
120views more  COMCOM 2002»
13 years 7 months ago
An interactive video delivery and caching system using video summarization
With the advance of high-speed network technologies, the availability and popularity of streaming media content over the Internet has grown rapidly in recent years. The delivery a...
Sung-Ju Lee, Wei-Ying Ma, Bo Shen