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EUC
2004
Springer
14 years 4 months ago
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
Seiichiro Fujii, Toshinori Sato
JLP
2007
95views more  JLP 2007»
13 years 10 months ago
Model checking a cache coherence protocol of a Java DSM implementation
Jackal is a fine-grained distributed shared memory implementation of the Java programming language. It aims to implement Java’s memory model and allows multithreaded Java progr...
Jun Pang, Wan Fokkink, Rutger F. H. Hofman, Ronald...
ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
14 years 7 months ago
Optimizing the Thermal Behavior of Subarrayed Data Caches
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
14 years 5 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISCA
2005
IEEE
121views Hardware» more  ISCA 2005»
14 years 4 months ago
Direct Cache Access for High Bandwidth Network I/O
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Ram Huggahalli, Ravi R. Iyer, Scott Tetrick