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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
13 years 11 months ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
ICSE
2000
IEEE-ACM
13 years 11 months ago
Dragonfly: linking conceptual and implementation architectures of multiuser interactive systems
Software architecture styles for developing multiuser applications are usually defined at a conceptual level, abstracting such low-level issues of distributed implementation as co...
Gary E. Anderson, T. C. Nicholas Graham, Timothy N...
SYSTOR
2009
ACM
14 years 2 months ago
DHIS: discriminating hierarchical storage
A typical storage hierarchy comprises of components with varying performance and cost characteristics, providing multiple options for data placement. We propose and evaluate a hie...
Chaitanya Yalamanchili, Kiron Vijayasankar, Erez Z...
CF
2009
ACM
14 years 2 months ago
A light-weight fairness mechanism for chip multiprocessor memory systems
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
Magnus Jahre, Lasse Natvig
VLSID
2006
IEEE
142views VLSI» more  VLSID 2006»
14 years 7 months ago
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors
- Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, ...
Nachiketh R. Potlapally, Srivaths Ravi, Anand Ragh...