243 search results - page 10 / 49 » Cache miss clustering for banked memory systems |
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
ISCA
2007
IEEE
13 years 7 months ago
2007
IEEE
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
ISCA
1993
IEEE
14 years 1 days ago
1993
IEEE
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
ICS
2003
Tsinghua U.
14 years 1 months ago
2003
Tsinghua U.
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remappi...