243 search results - page 30 / 49 » Cache miss clustering for banked memory systems |
SIGMETRICS
1996
ACM
14 years 2 days ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...
EUROSYS
2007
ACM
14 years 5 months ago
2007
ACM
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
CDES
2008
13 years 9 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...