243 search results - page 8 / 49 » Cache miss clustering for banked memory systems |
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
CAL
2010
13 years 5 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...
CONCURRENCY
2006
13 years 8 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
ASPLOS
1996
ACM
14 years 1 days ago
1996
ACM
This paper describes Shasta, a system that supports a shared address space in software on clusters of computers with physically distributed memory. A unique aspect of Shasta compa...