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SC
1995
ACM
13 years 11 months ago
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
Umakishore Ramachandran, Gautam Shah, Anand Sivasu...
HPCA
2009
IEEE
14 years 8 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
SPAA
2009
ACM
14 years 8 months ago
Beyond nested parallelism: tight bounds on work-stealing overheads for parallel futures
Work stealing is a popular method of scheduling fine-grained parallel tasks. The performance of work stealing has been extensively studied, both theoretically and empirically, but...
Daniel Spoonhower, Guy E. Blelloch, Phillip B. Gib...
ASPLOS
2010
ACM
14 years 2 months ago
Addressing shared resource contention in multicore processors via scheduling
Contention for shared resources on multicore processors remains an unsolved problem in existing systems despite significant research efforts dedicated to this problem in the past...
Sergey Zhuravlev, Sergey Blagodurov, Alexandra Fed...
DAC
2007
ACM
14 years 8 months ago
Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...
Yongsoo Joo, Youngjin Cho, Donghwa Shin, Naehyuck ...