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DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 3 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
ICS
2003
Tsinghua U.
14 years 2 months ago
Predictive dynamic thermal management for multimedia applications
Dynamic Thermal Management (DTM) techniques have been proposed to save on thermal packaging and cooling costs for generalpurpose processors. However, when invoked, these technique...
Jayanth Srinivasan, Sarita V. Adve
ICCD
2001
IEEE
140views Hardware» more  ICCD 2001»
14 years 5 months ago
Cost-effective Hardware Acceleration of Multimedia Applications
General-purpose microprocessors augmented with SIMD execution units enhance multimedia applications by exploiting data level parallelism. However, supporting/overhead related inst...
Deependra Talla, Lizy Kurian John
VLDB
2001
ACM
104views Database» more  VLDB 2001»
14 years 1 months ago
Cache Fusion: Extending Shared-Disk Clusters with Shared Caches
Cache Fusion TM is a fundamental component of Oracle’s Real Application Cluster configuration, a shared-cache clustered-database architecture that transparently extends databas...
Tirthankar Lahiri, Vinay Srihari, Wilson Chan, N. ...
GLVLSI
2008
IEEE
137views VLSI» more  GLVLSI 2008»
14 years 3 months ago
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
Ann Gordon-Ross, Jeremy Lau, Brad Calder