26 search results - page 5 / 6 » Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power |
CSREAESA
2003
13 years 8 months ago
2003
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
DATE
2010
IEEE
14 years 16 days ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
LCTRTS
2009
Springer
14 years 2 months ago
2009
Springer
Multicores are becoming ubiquitous, not only in general-purpose but also embedded computing. This trend is a reflexion of contemporary embedded applications posing steadily incre...