55 search results - page 7 / 11 » Caches and Hash Trees for Efficient Memory Integrity |
AAAI
2006
13 years 8 months ago
2006
AND/OR search spaces have recently been introduced as a unifying paradigm for advanced algorithmic schemes for graphical models. The main virtue of this representation is its sens...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
CLUSTER
2008
IEEE
13 years 9 months ago
2008
IEEE
Efficient intra-node shared memory communication is important for High Performance Computing (HPC), especially with the emergence of multi-core architectures. As clusters continue ...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...