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MICRO
2008
IEEE
146views Hardware» more  MICRO 2008»
13 years 8 months ago
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
Dynamically tracking the flow of data within a microprocessor creates many new opportunities to detect and track malicious or erroneous behavior, but these schemes all rely on the...
Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jo...
ICPP
2009
IEEE
14 years 3 months ago
Complexity Analysis and Performance Evaluation of Matrix Product on Multicore Architectures
The multicore revolution is underway, bringing new chips introducing more complex memory architectures. Classical algorithms must be revisited in order to take the hierarchical me...
Mathias Jacquelin, Loris Marchal, Yves Robert
MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
14 years 2 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
ACSAC
2003
IEEE
14 years 1 months ago
Isolated Program Execution: An Application Transparent Approach for Executing Untrusted Programs
In this paper, we present a new approach for safe execution of untrusted programs by isolating their effects from the rest of the system. Isolation is achieved by intercepting fi...
Zhenkai Liang, V. N. Venkatakrishnan, R. Sekar
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
14 years 15 hour ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...