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EUROPAR
2000
Springer
13 years 11 months ago
Cache Remapping to Improve the Performance of Tiled Algorithms
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...
Kristof Beyls, Erik H. D'Hollander
ICS
2005
Tsinghua U.
14 years 1 months ago
The implications of working set analysis on supercomputing memory hierarchy design
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
Richard C. Murphy, Arun Rodrigues, Peter M. Kogge,...
IPPS
2007
IEEE
14 years 1 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
EUROPAR
2000
Springer
13 years 11 months ago
Automatic Generation of Block-Recursive Codes
Abstract. Block-recursive codes for dense numerical linear algebra computations appear to be well-suited for execution on machines with deep memory hierarchies because they are e e...
Nawaaz Ahmed, Keshav Pingali
ISCI
2000
79views more  ISCI 2000»
13 years 7 months ago
Data block prefetching and caching in a hierarchical storage model
Storage subsystems have become one of the most important components in computer systems nowadays and have been expanded to include all three levels of memory hierarchy, namely the...
Athena Vakali