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GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 5 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...
LCPC
2005
Springer
14 years 1 months ago
Automatic Measurement of Instruction Cache Capacity
There is growing interest in autonomic computing systems that can optimize their own behavior on different platforms without manual intervention. Examples of successful self-opti...
Kamen Yotov, Sandra Jackson, Tyler Steele, Keshav ...
MICRO
2008
IEEE
146views Hardware» more  MICRO 2008»
13 years 7 months ago
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
Dynamically tracking the flow of data within a microprocessor creates many new opportunities to detect and track malicious or erroneous behavior, but these schemes all rely on the...
Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jo...
WWW
2008
ACM
14 years 8 months ago
Performance of compressed inverted list caching in search engines
Due to the rapid growth in the size of the web, web search engines are facing enormous performance challenges. The larger engines in particular have to be able to process tens of ...
Jiangong Zhang, Xiaohui Long, Torsten Suel
ISCA
1998
IEEE
129views Hardware» more  ISCA 1998»
13 years 11 months ago
Memory System Characterization of Commercial Workloads
Commercial applications such as databases and Web servers constitute the largest and fastest-growing segment of the market for multiprocessor servers. Ongoing innovations in disk ...
Luiz André Barroso, Kourosh Gharachorloo, E...