267 search results - page 44 / 54 » Caching in Web memory hierarchies |
FPGA
2004
ACM
14 years 28 days ago
2004
ACM
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
ICS
2000
Tsinghua U.
13 years 11 months ago
2000
Tsinghua U.
Loop fusion is important to optimizing compilers because it is an important tool in managing the memory hierarchy. By fusing loops that use the same data elements, we can reduce t...
USENIX
1993
13 years 8 months ago
1993
Robotic storage devices offer huge storage capacity at a low cost per byte, but with large access times. Integrating these devices into the storage hierarchy presents a challenge ...
CASES
2004
ACM
14 years 29 days ago
2004
ACM
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy...
PPOPP
1999
ACM
13 years 12 months ago
1999
ACM
Divide and conquer algorithms are a good match for modern parallel machines: they tend to have large amounts of inherent parallelism and they work well with caches and deep memory...