59 search results - page 6 / 12 » Caching of interactive multiple choice MPEG-4 presentations |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
CC
2010
Springer
14 years 1 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
DATE
2005
IEEE
14 years 22 days ago
2005
IEEE
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
ICSE
2008
IEEE-ACM
14 years 7 months ago
2008
IEEE-ACM
We present a tool for performance modeling of Service Oriented Architectures (SOAs). As mission-critical use of whole-ofgovernment SOAs become pervasive, the capability to model a...
ICSE
2009
IEEE-ACM
14 years 8 months ago
2009
IEEE-ACM
Designers of concurrent programs are faced with many choices of synchronization mechanisms, among which clear functional trade-offs exist. Making synchronization customizable is h...