169 search results - page 2 / 34 » Caching queues in memory buffers |
TON
2008
13 years 10 months ago
2008
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
DATE
2004
IEEE
14 years 2 months ago
2004
IEEE
ISCA
2005
IEEE
14 years 4 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
VLDB
1997
ACM
14 years 3 months ago
1997
ACM
Abstract. Recent results in the Rio project at the University of Michigan show that it is possible to create an area of main memory that is as safe as disk from operating system cr...
WMPI
2004
ACM
14 years 4 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...