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ISCC
2009
IEEE
163views Communications» more  ISCC 2009»
14 years 4 months ago
Distributed parallel scheduling algorithms for high-speed virtual output queuing switches
Abstract—This paper presents a novel scalable switching architecture for input queued switches with its proper arbitration algorithms. In contrast to traditional switching archit...
Lotfi Mhamdi, Mounir Hamdi
MICRO
2008
IEEE
114views Hardware» more  MICRO 2008»
14 years 4 months ago
Toward a multicore architecture for real-time ray-tracing
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting intera...
Venkatraman Govindaraju, Peter Djeu, Karthikeyan S...
NN
2002
Springer
144views Neural Networks» more  NN 2002»
13 years 9 months ago
Projective ART for clustering data sets in high dimensional spaces
A new neural network architecture (PART) and the resulting algorithm are proposed to
Yongqiang Cao, Jianhong Wu
FPL
2004
Springer
99views Hardware» more  FPL 2004»
14 years 3 months ago
A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development
A novel configuration bitstream generation tool for a custom FPGA platform is presented. It can support a variety of devices of similar architecture. The tool exhibits technology i...
K. Siozios, George Koutroumpezis, Konstantinos Tat...
TPDS
2010
174views more  TPDS 2010»
13 years 8 months ago
Parallel Two-Sided Matrix Reduction to Band Bidiagonal Form on Multicore Architectures
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
Hatem Ltaief, Jakub Kurzak, Jack Dongarra