Sciweavers

4809 search results - page 63 / 962
» CajunBot: Architecture and algorithms
Sort
View
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
16 years 24 days ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
HPCC
2007
Springer
16 years 6 days ago
Adaptive Computation of Self Sorting In-Place FFTs on Hierarchical Memory Architectures
Computing ”in-place and in-order”FFT poses a very difficult problem on hierarchical memory architectures where data movement can seriously degrade the performance. In this pape...
Ayaz Ali, S. Lennart Johnsson, Jaspal Subhlok
IPPS
2006
IEEE
16 years 2 days ago
A multiprocessor architecture for the massively parallel model GCA
The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical...
Wolfgang Heenes, Rolf Hoffmann, Johannes Jendrsczo...
ACMSE
2006
ACM
16 years 23 hour ago
HELLAS: a specialized architecture for interactive deformable object modeling
Applications involving interactive modeling of deformable objects require highly iterative, floating-point intensive numerical simulations. As the complexity of these models incr...
Shrirang M. Yardi, Benjamin Bishop, Thomas P. Kell...
ANCS
2005
ACM
15 years 11 months ago
A novel reconfigurable hardware architecture for IP address lookup
IP address lookup is one of the most challenging problems of Internet routers. In this paper, an IP lookup rate of 263 Mlps (Million lookups per second) is achieved using a novel ...
Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabae...