Sciweavers

4809 search results - page 782 / 962
» CajunBot: Architecture and algorithms
Sort
View
DAC
2007
ACM
15 years 10 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley
DAC
2010
ACM
15 years 9 months ago
Reducing the number of lines in reversible circuits
Reversible logic became a promising alternative to traditional circuits because of its applications e.g. in low-power design and quantum computation. As a result, design of revers...
Robert Wille, Mathias Soeken, Rolf Drechsler
DAC
2010
ACM
15 years 9 months ago
Representative path selection for post-silicon timing prediction under variability
The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we...
Lin Xie, Azadeh Davoodi
ERLANG
2007
ACM
15 years 9 months ago
An Erlang framework for autonomous mobile robots
This paper presents an Erlang-based framework, developed by the authors, for the realisation of software systems for autonomous mobile robots. On the basis of the analysis of the ...
Corrado Santoro
DAC
2009
ACM
15 years 9 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen