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CODES
2005
IEEE
15 years 11 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung
174
Voted
DAGM
2005
Springer
15 years 11 months ago
Rapid Online Learning of Objects in a Biologically Motivated Recognition Architecture
We present an approach for the supervised online learning of object representations based on a biologically motivated architecture of visual processing. We use the output of a rece...
Stephan Kirstein, Heiko Wersing, Edgar Körner
ISMIR
2004
Springer
126views Music» more  ISMIR 2004»
15 years 11 months ago
Tools and Architecture for the Evaluation of Similarity Measures : Case Study of Timbre Similarity
The systematic testing of the very many parameters and algorithmic variants involved in the design of high-level music descriptors at large, and similarity measure in particular, ...
Jean-Julien Aucouturier, François Pachet
ISADS
2003
IEEE
15 years 11 months ago
The Central Guardian Approach to Enforce Fault Isolation in the Time-Triggered Architecture
This paper discusses measures to make a distributed system based on the Time-Triggered Architecture resistant to arbitrary node failures. To achieve this, the presented approach i...
Günther Bauer, Hermann Kopetz, Wilfried Stein...
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
15 years 10 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...