Novel architecture for loop acceleration: a case study

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor ap

• Type: Conference
• Year: 2005
• Where: CODES
• Authors: Seng Lin Shee, Sri Parameswaran, Newton Cheung
• Keywords: CODES 2005, Coprocessor, Custom Coprocessor, Custom Coprocessor Approach, Hardware-Software Codesign