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SIGCOMM
2009
ACM
16 years 21 days ago
SmartRE: an architecture for coordinated network-wide redundancy elimination
Application-independent Redundancy Elimination (RE), or identifying and removing repeated content from network transfers, has been used with great success for improving network pe...
Ashok Anand, Vyas Sekar, Aditya Akella
CODES
2005
IEEE
15 years 11 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
PLDI
2004
ACM
15 years 11 months ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
IPPS
2003
IEEE
15 years 11 months ago
Phylogenetic Tree Inference on PC Architectures with AxML/PAxML
Inference of phylogenetic trees comprising hundreds or even thousands of organisms based on the maximum likelihood method is computationally extremely expensive. In previous work,...
Alexandros Stamatakis, Thomas Ludwig 0002
EUROPAR
2009
Springer
15 years 10 months ago
Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...
Cédric Augonnet, Samuel Thibault, Raymond N...