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RTSS
2003
IEEE
14 years 2 months ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
CODES
2007
IEEE
14 years 3 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
RTCSA
2003
IEEE
14 years 2 months ago
Deterministic and Statistical Deadline Guarantees for a Mixed Set of Periodic and Aperiodic Tasks
Current hard real-time technologies are unable to support a new class of applications that have real-time constraints but with dynamic request arrivals and unpredictable resource r...
Minsoo Ryu, Seongsoo Hong
CSE
2011
IEEE
12 years 8 months ago
Parallel Execution of AES-CTR Algorithm Using Extended Block Size
—Data encryption and decryption are common operations in a network based application programs with security. In order to keep pace with the input data rate in such applications, ...
Nhat-Phuong Tran, Myungho Lee, Sugwon Hong, Seung-...
ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
14 years 5 days ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim