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FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 2 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...
CODES
2004
IEEE
14 years 24 days ago
System-on-chip validation using UML and CWL
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo...
C++
1992
83views more  C++ 1992»
13 years 10 months ago
Adding Concurrency to a Programming Language
A programming language that lacks facilities for concurrent programming can gain those facilities in two ways: the language can be extended with additional constructs, which will ...
Peter A. Buhr, G. Ditchfeld
SIGCOMM
1996
ACM
14 years 1 months ago
Measuring the Performance of Communication Middleware on High-Speed Networks
Conventional implementations of communication middleware (such as CORBA and traditional RPC toolkits) incur considerable overhead when used for performance-sensitive applications ...
Aniruddha S. Gokhale, Douglas C. Schmidt
DDECS
2008
IEEE
227views Hardware» more  DDECS 2008»
13 years 10 months ago
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator
The paper introduces a cryptographic System on a Chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is bui...
Milos Drutarovsky, Michal Varchola