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133
Voted
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
15 years 9 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
158
Voted
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
15 years 9 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
100
Voted
GTTSE
2007
Springer
15 years 8 months ago
Model Transformations for the Compilation of Multi-processor Systems-on-Chip
With the increase of amount of transistors which can be contained on a chip and the constant expectation for more sophisticated applications, the design of Systems-on-Chip (SoC) is...
Éric Piel, Philippe Marquet, Jean-Luc Dekey...
140
Voted
ERSHOV
2006
Springer
15 years 6 months ago
Streaming Networks for Coordinating Data-Parallel Programs
A new coordination language for distributed data-parallel programs is presented, call SNet. The intention of SNet is to introduce advanced structuring techniques into a coordinatio...
Clemens Grelck, Sven-Bodo Scholz, Alexander V. Sha...
138
Voted
TC
2010
15 years 29 days ago
Scalable Node-Level Computation Kernels for Parallel Exact Inference
—In this paper, we investigate data parallelism in exact inference with respect to arbitrary junction trees. Exact inference is a key problem in exploring probabilistic graphical...
Yinglong Xia, Viktor K. Prasanna