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» Can Parallel Algorithms Enhance Serial Implementation
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FPGA
2009
ACM
343views FPGA» more  FPGA 2009»
14 years 2 months ago
Fpga-based face detection system using Haar classifiers
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kas...
IPPS
2006
IEEE
14 years 1 months ago
MegaProto/E: power-aware high-performance cluster with commodity technology
In our research project named “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, we have been developing a prototype cluster not based on ASIC or FPGA...
Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, H...
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 4 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
EUROPAR
2005
Springer
14 years 1 months ago
Hierarchical Scheduling for Moldable Tasks
The model of moldable task (MT) was introduced some years ago and has been proved to be an efficient way for implementing parallel applications. It considers a target application ...
Pierre-François Dutot
ICCCN
2007
IEEE
14 years 2 months ago
Utility-Based Routing in Communication Networks with Unstable Links
Abstract—Traditional Dijkstra and Bellman-Ford routing algorithms can only provide the best route to each destination based on a fixed link cost model. We propose a utility-base...
Mingming Lu, Jie Wu