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DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 7 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
ICS
2010
Tsinghua U.
13 years 9 months ago
InterferenceRemoval: removing interference of disk access for MPI programs through data replication
As the number of I/O-intensive MPI programs becomes increasingly large, many efforts have been made to improve I/O performance, on both software and architecture sides. On the sof...
Xuechen Zhang, Song Jiang
DSD
2010
IEEE
112views Hardware» more  DSD 2010»
13 years 6 months ago
Re-NUCA: Boosting CMP Performance Through Block Replication
— Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have co...
Pierfrancesco Foglia, Cosimo Antonio Prete, Marco ...
ICPP
1999
IEEE
13 years 11 months ago
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
Jim Nilsson, Fredrik Dahlgren
SIGMOD
1998
ACM
140views Database» more  SIGMOD 1998»
13 years 11 months ago
Caching Multidimensional Queries Using Chunks
Caching has been proposed (and implemented) by OLAP systems in order to reduce response times for multidimensional queries. Previous work on such caching has considered table leve...
Prasad Deshpande, Karthikeyan Ramasamy, Amit Shukl...