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MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 2 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
MOBISYS
2007
ACM
14 years 7 months ago
Improving mobile database access over wide-area networks without degrading consistency
We report on the design, implementation, and evaluation of a system called Cedar that enables mobile database access with good performance over low-bandwidth networks. This is acc...
Niraj Tolia, Mahadev Satyanarayanan, Adam Wolbach
ICS
1999
Tsinghua U.
13 years 11 months ago
Performance impact of proxies in data intensive client-server applications
Large client-server data intensive applications can place high demands on system and network resources. This is especially true when the connection between the client and server s...
Michael D. Beynon, Alan Sussman, Joel H. Saltz
HPCA
2001
IEEE
14 years 7 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
CLUSTER
2006
IEEE
14 years 1 months ago
Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
Lei Chai, Albert Hartono, Dhabaleswar K. Panda